Among known clock ride-over circuits, there are a circuit described in Japanese Patent Kokai Publication JP-A-4-96535, as shown in FIG. 7 herein, and an FIFO employing a RAM of FIG. 9, as described in a publication by Y. Hasegawa entitled: “Introduction to Hardware Designing by VHDL”. The entire disclosures of these publications are incorporated herein by reference thereto. The operating waveforms of the circuits of FIGS. 7 and 9 are shown in FIGS. 8 and 10, respectively.
The circuit of FIG. 7 is designed so that a write timing signal WT 18 operates as an operation control input to a JK flipflop 24 and so that input data 17 obtained on serial/parallel conversion is stored in a distributed fashion in an odd register 27 and in an even register 28. In a readout register selection timing control circuit 33, an output of the JK flipflop 24 is shifted by a readout clock CLK_r 21 to generate three different signals, namely a LEAD 34, representing a lead phase, a NORM 35, representing a reference phase and a LAG 36 representing a lag phase. On power up, a phase detection circuit 26 checks which one of the three phases LEAD, NORM and
LAG is the phase of the write timing signal WT 18 or the phase of a readout timing signal RT 20, with a D-flipflop keeping to hold the verified state. Since the transition point between LEAD, NORM and LAG is in a domain where the output of the odd register 27 and that of the even register 28 are stable, the contents of the odd register 27 and the even register 28 can be read out in stability with the readout timing signal RT 20.
Although the FIFO shown in FIG. 9 represents an illustrative application to logical synthesis, the architecture is a example of a routine FIFO. The configuration of FIG. 9 has an internal RAM 45, the addresses for which are generated by a write counter WP 43 and a readout counter RP 44 to effect writing and readout. In the embodiment shown in FIG. 9, FULL 41 and EMPTY 43 are output as status signals for the RAM. The FULL 41 and EMPTY 43 operate for preventing the overflow and the underflow, respectively. Although one clock route is shown in FIG. 9, the basic structure remains unchanged if two clock routes are used each for write and readout.